After Drawing a Schematic Graph in Xilinx ISE 14.7 as the following and trying to Check Design Rules, I got the following errors.
And this is my Schematic Graph
It turns out that the wires connected to the graph should be an element of the output array. To put it in another way, the wires connected to the bus should be from Y(0) to Y(7), in accordance to the output Y(0:7).
I renamed all the wires, and now it works.
Many thanks to Ref. 1!